Computing devices such as smartphones have become common in modern society. The prevalence of computing devices may be attributed to the many functions that are enabled within such computing devices. As the computing devices evolve, there is an increased need for high performance active devices that are provided on various substrates along with other semiconductor components to form various types of circuits. These high performance active devices often act as relays, and are generally referred to as micro-electro-mechanical system (MEMS) devices. MEMS devices are currently being considered in many radio frequency (RF) applications, such as antenna switches, load switches, transmit/receive switches, tuning switches, and the like.
Increasingly complex packaging solutions have been designed and manufactured to provide greater functionality in computing devices. Final packaging solutions of the computing devices may be provided as two-dimensional (2D) packaging solutions or three-dimensional (3D) packaging solutions. In this regard, FIG. 1A is a schematic diagram of an exemplary 2D packaging solution 10 comprising a MEMS substrate 12 disposed side-by-side of an application-specific integrated circuit (ASIC) 14.
With reference to FIG. 1A, the MEMS substrate 12 and the ASIC 14 are provided on a laminate 16. The MEMS substrate 12 is bonded to a cap wafer 18. A cavity 20 is formed between the cap wafer 18 and the MEMS substrate 12 to encapsulate one or more MEMS devices (not shown). The MEMS substrate 12 and the ASIC 14 are electrically coupled to the laminate 16 by bonding wires 22 and 24, respectively. The MEMS substrate 12 is electrically coupled to the ASIC 14 via a bonding wire 26. An over molding layer 28 is provided in the 2D packaging solution 10 to protect the bonding wires 22, 24, and 26. The over molding layer 28 covers the MEMS substrate 12, the cap wafer 18, and the ASIC 14 in the 2D packaging solution 10.
Because the MEMS substrate 12 and the ASIC 14 are disposed side-by-side on the laminate 16, the 2D packaging solution 10 has a relatively larger footprint. In addition, the over molding layer 28 increases the height of the 2D packaging solution 10. In this regard, FIG. 1B is a schematic diagram of an exemplary 3D packaging solution 30 wherein the MEMS substrate 12 and the ASIC 14 are stacked to have a reduced footprint as compared to the footprint of the 2D packaging solution 10 of FIG. 1A. Common elements between FIGS. 1A and 1B are shown therein with common element numbers and will not be re-described herein.
The MEMS substrate 12 in the 3D packaging solution 30 comprises at least one conductive through glass via (TGV) 31 that electrically couples the MEMS substrate 12 to the laminate 16 using at least one conductive pad 32. As illustrated in FIG. 1B, a bonding wire 33 is still required to electrically couple the ASIC 14 to the at least one TGV 31 in the MEMS substrate 12. The laminate 16 is electrically coupled to at least one solderable pad 34. Accordingly, an over molding layer 35 is also required to protect the bonding wire 33. As a result, the 3D packaging solution 30 may have an increased height as compared to the height of the 2D packaging solution 10 of FIG. 1A. In this regard, FIG. 1C is a schematic diagram of an exemplary 3D packaging solution 36 configured to have a reduced height as compared to the height of the 3D packaging solution 30 of FIG. 1B by eliminating the bonding wire 33 and the over molding layer 35. Common elements between FIGS. 1A and 1C are shown therein with common element numbers and will not be re-described herein.
As illustrated in FIG. 1C, a MEMS device 38 is provided on a conductive stack(s) 40 that is conductively bonded to the MEMS substrate 12. The conductive stack(s) 40 is electrically coupled to conductive bonding structures 42(1)-42(4), which are electrically coupled to the ASIC 14 by at least one conductive via 44. By utilizing the at least one conductive via 44 in the cap wafer 18, it is possible to eliminate the bonding wire 33 and the over molding layer 35 in the 3D packaging solution 30 of FIG. 1B by implementing wafer level chip scale packaging (WLCSP) bumps 45, thus having a reduced height in the 3D packaging solution 36 as compared to the height of the 3D packaging solution 30.